In digital baseband communication networks, the data sampling clock is usually recovered from the incoming data stream because no separate clock signal is provided. In many such communication systems, phase locked loops (PLLs) are used for locally maintaining in remote stations a clock signal that corresponds in frequency and phase to the clock of data signals that were transmitted through the network and received by the station. The difference between the local clock signal and that recovered from received data is monitored and the phase or frequency of the local clock is adapted and "locked" to that of the received data signal, or is maintained at the last status as long as no data are available or received.
Phase locked loop circuits were first implemented in analog technique. The basic design includes a phase detector, a loop filter, and a voltage controlled oscillator (VCO). The phase detector determines the phase error between the incoming data and the VCO output signal. The loop filter, in response to the phase error signal, generates a control signal for the VCO.
In a digital environment, digital PLLs are clearly preferred because they can be implemented easier in LSI techniques than analog PLLs. Many different digital PLL schemes were designed. A general survey is given in an article by W. C. Lindsay et al.: "Survey of Digital Phase-Locked Loops", Proceedings of the IEEE, Vol. 69, No. 4, April 1981, pp. 410-431.
The digital nature of the conventional phase detector which is used in digital PLLs requires, because of serial sampling, a control clock frequency which is n times higher than the data clock to be processed, where n is the number of discrete phase values which the detector can distinguish (usually n=16). This constraint limits the application of digital PLLs to low data rate transmission systems.
Various phase locked loop circuits and clock signal phase shifting circuits were described in the literature, and a selection of such known circuit descriptions is listed and briefly analyzed below.
W. C. Leung: Digital phase-locked loop circuit. IBM Technical Disclosure Bulletin, Vol. 18, No. 10, March 1976, pp. 3334-3337. This article describes a PLL which uses shift registers and selection logic to obtain a variable delay. The shift registers must operate at much higher speed than the generated clock frequency.
M. E. Homan: Electronically adjustable computer clocking system. IBM Technical Disclosure Bulletin, Vol. 15, No. 1, June 1972, pp. 252-254. This publication discloses an arrangement comprising a tapped delay chain with selection logic to obtain a variable phase shift, but it does not provide for the detection of a phase error between a clock and a data signal for controlling a phase error correction of the clock signal.
L. A. Laurich et al.: Phase lock loop with delay line oscillator. IBM Technical Disclosure Bulletin, Vol. 13, No. 7, December 1970, pp. 1863-1864. The PLL described in this article uses tapped delay lines as clock oscillator components, and it has a counter for clock oscillator pulses and stores the counter contents as error indication under control of input data. Outputs of the tapped delay lines are selected in response to the error indication for changing the oscillator frequency. The counter and some of the evaluation circuitry must operate at a speed which is a multiple of the generated clock frequency.
L. A. Laurich: Phase lock loop with variable delay line generator. IBM Technical Disclosure Bulletin, Vol. 13, No. 7, December 1970, pp. 1861-1862. This publication also discloses a PLL which uses tapped delay lines as oscillator components controlled by logic to selectively change the oscillator frequency. Pulses from a master oscillator are furnished to a two-stage shift register between occurrences of clock signal and data signal transitions, thus obtaining an error indication which controls the tap selection logic. All digital elements must operate at a multiple speed of the data clock.